80 lines
1.3 KiB
Systemverilog
80 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2004 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc;
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initial cyc = 1;
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reg [125:0] a;
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wire q;
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sub sub (
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.q(q),
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.a(a),
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.clk(clk)
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);
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always @(posedge clk) begin
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if (cyc != 0) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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a <= 126'b1000;
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end
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if (cyc == 2) begin
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a <= 126'h1001;
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end
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if (cyc == 3) begin
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a <= 126'h1010;
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end
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if (cyc == 4) begin
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a <= 126'h1111;
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if (q !== 1'b0) $stop;
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end
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if (cyc == 5) begin
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if (q !== 1'b1) $stop;
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end
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if (cyc == 6) begin
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if (q !== 1'b0) $stop;
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end
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if (cyc == 7) begin
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if (q !== 1'b0) $stop;
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end
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if (cyc == 8) begin
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if (q !== 1'b0) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module sub (
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input clk,
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input [125:0] a,
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output reg q
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);
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// verilator public_module
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reg [125:0] g_r;
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wire [127:0] g_extend = {g_r, 1'b1, 1'b0};
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reg [6:0] sel;
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wire g_sel = g_extend[sel];
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always @(posedge clk) begin
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g_r <= a;
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sel <= a[6:0];
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q <= g_sel;
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end
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endmodule
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