41 lines
764 B
Systemverilog
41 lines
764 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2012 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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integer i;
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integer a_var;
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sub sub ();
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task nottask();
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endtask
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function int notfunc();
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return 0;
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endfunction
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initial begin
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nf = 0; // z not found
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sub.subsubz.inss = 0; // subsub not found
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i = nofunc(); // nofunc not found
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i = sub.nofuncs(); // nofuncs not found
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notask(); // notask not found
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a_var(); // Calling variable as task
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$finish;
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end
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endmodule
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module sub;
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subsub subsub ();
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function int notfuncs();
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return 0;
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endfunction
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endmodule
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module subsub;
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integer inss;
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endmodule
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