77 lines
1.4 KiB
Systemverilog
77 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk,
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input reset_l
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);
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reg inmod;
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generate
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if (1) begin
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// Traces as genblk1.ingen
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integer ingen;
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initial $display("ingen: {mod}.genblk1 %m");
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end
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endgenerate
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integer rawmod;
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initial begin
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begin
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integer upa;
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begin : d3nameda
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// %m='.d3nameda' var=_unnamed#.d3nameda.b1
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integer d3a;
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$display("d3a: {mod}.d3nameda %m");
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end
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end
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end
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initial begin
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integer b2;
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$display("b2: {mod} %m");
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begin : b3named
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integer b3n;
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$display("b3n: {mod}.b3named: %m");
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end
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if (1) begin
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integer b3;
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$display("b3: {mod} %m");
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if (1) begin
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begin
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begin
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begin
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integer b4;
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$display("b4: {mod} %m");
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end
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end
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end
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end
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else begin
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integer b4;
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$display("bb %m");
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end
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end
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else begin
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integer b4;
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$display("b4 %m");
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end
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tsk;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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task automatic tsk;
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integer t1;
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$display("t1 {mod}.tsk %m");
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begin
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integer t2;
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$display("t2 {mod}.tsk %m");
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end
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endtask
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endmodule
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