70 lines
1.4 KiB
Systemverilog
70 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2008 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc = 0;
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integer v;
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reg i;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire oa; // From a of a.v
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wire oz; // From z of z.v
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// End of automatics
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a a (.*);
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z z (.*);
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d i=%x oa=%x oz=%x\n", $time, cyc, i, oa, oz);
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`endif
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cyc <= cyc + 1;
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i <= cyc[0];
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if (cyc == 0) begin
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v = 3;
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if (v !== 3) $stop;
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if (assignin(v) !== 2) $stop;
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if (v !== 3) $stop; // Make sure V didn't get changed
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end
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else if (cyc < 10) begin
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if (cyc == 11 && oz !== 1'b0) $stop;
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if (cyc == 12 && oz !== 1'b1) $stop;
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if (cyc == 12 && oa !== 1'b1) $stop;
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end
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else if (cyc < 90) begin
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end
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else if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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function integer assignin(input integer i);
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i = 2;
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assignin = i;
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endfunction
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endmodule
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module a (
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input i,
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output oa
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);
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// verilator lint_off ASSIGNIN
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assign i = 1'b1;
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assign oa = i;
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endmodule
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module z (
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input i,
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output oz
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);
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assign oz = i;
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endmodule
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