27 lines
531 B
Systemverilog
27 lines
531 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t ( /*AUTOARG*/
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// Outputs
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zeros,
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// Inputs
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num
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);
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parameter WIDTH = 1;
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input logic [WIDTH-1:0] num;
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output logic [$clog2(WIDTH+1)-1:0] zeros;
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integer i;
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always_comb begin
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i = 0;
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while ((i < WIDTH) & ~num[WIDTH-1-i]) i = i + 1;
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zeros = i[$clog2(WIDTH+1)-1 : 0];
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end
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endmodule
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