16 lines
352 B
Systemverilog
16 lines
352 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2019 Driss Hafdi
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// SPDX-License-Identifier: CC0-1.0
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module t;
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localparam logic [7:0] TOO_FEW[5] = '{0, 1, 2 ** 8 - 1}; // Bad
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initial begin
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$display("%p", TOO_FEW);
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$stop;
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end
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endmodule
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