50 lines
749 B
Systemverilog
50 lines
749 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Michael Bikovitsky
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// SPDX-License-Identifier: CC0-1.0
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module t;
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wire true1;
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not1 a(true1, '0);
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wire false1;
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not1 b(false1, '1);
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wire true2;
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not1 c(true2, '0);
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wire false2;
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not1 d(false2, '1);
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initial begin
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if (true1 != '1) $stop;
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if (false1 != '0) $stop;
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if (true2 != '1) $stop;
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if (false2 != '0) $stop;
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$finish;
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end
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endmodule
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primitive not1(q, d);
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output q;
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input d;
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table
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0 : 1;
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1 : 0;
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x : x;
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endtable
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endprimitive
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primitive not2(q, d);
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output q;
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input d;
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table
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0 : 1;
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1 : 0;
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X : X;
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endtable
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endprimitive
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