20 lines
430 B
Systemverilog
20 lines
430 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2018 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module top (
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input d,
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output ext0,
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output ext1,
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output extx,
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output extz
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);
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assign ext0 = (d === 1'b0);
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assign ext1 = (d === 1'b1);
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assign extx = (d === 1'bx);
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assign extz = (d === 1'bz);
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endmodule
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