114 lines
1.2 KiB
Plaintext
114 lines
1.2 KiB
Plaintext
$date
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Sat Mar 14 09:17:00 2026
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$end
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$version
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Generated by VerilatedFst
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$end
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$timescale
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1ps
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$end
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$scope module top $end
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$var wire 1 ! clk $end
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$scope module t $end
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$var wire 1 ! clk $end
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$var integer 32 " cyc [31:0] $end
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$var logic 1 # a $end
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$var logic 1 $ b $end
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$var logic 1 % z $end
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$scope module sub_t_i $end
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$var wire 1 # x $end
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$var wire 1 $ y $end
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$var wire 1 % z $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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0%
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0$
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0#
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b00000000000000000000000000000000 "
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0!
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$end
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#10
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1!
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b00000000000000000000000000000001 "
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#15
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0!
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#20
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1!
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b00000000000000000000000000000010 "
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1#
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#25
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0!
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#30
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1!
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0#
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b00000000000000000000000000000011 "
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1$
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#35
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0!
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#40
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1!
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b00000000000000000000000000000100 "
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1#
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1%
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#45
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0!
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#50
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1!
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0%
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0#
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b00000000000000000000000000000101 "
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0$
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#55
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0!
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#60
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1!
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b00000000000000000000000000000110 "
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1#
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#65
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0!
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#70
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1!
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0#
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b00000000000000000000000000000111 "
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1$
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#75
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0!
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#80
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1!
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b00000000000000000000000000001000 "
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1#
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1%
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#85
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0!
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#90
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1!
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0%
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0#
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b00000000000000000000000000001001 "
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0$
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#95
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0!
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#100
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1!
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b00000000000000000000000000001010 "
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1#
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#105
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0!
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#110
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1!
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0#
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b00000000000000000000000000001011 "
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1$
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#115
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0!
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#120
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1!
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b00000000000000000000000000001100 "
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1#
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1%
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