69 lines
1.1 KiB
Systemverilog
69 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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`ifdef TOP
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module t (
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input clk
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);
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logic [7:0] in0 = 8'd020;
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logic [7:0] in1 = 8'd100;
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wire [7:0] out0;
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wire [7:0] out1;
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int count = 0;
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sub0 i_sub0 (
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.clk(clk),
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.in(in0),
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.out(out0)
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);
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sub1 i_sub1 (
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.clk(clk),
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.in(in1),
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.out(out1)
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);
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always_ff @(posedge clk) begin
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count <= count + 1;
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in0 <= in0 + 8'd1;
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in1 <= in1 + 8'd2;
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if (count == 3) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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`endif
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`ifdef SUB0
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module sub0 (
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input wire clk,
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input wire [7:0] in,
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output wire [7:0] out
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);
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logic [7:0] ff;
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always_ff @(posedge clk) ff <= in + 8'd1;
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assign out = ff;
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endmodule
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`endif
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`ifdef SUB1
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module sub1 (
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input wire clk,
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input wire [7:0] in,
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output wire [7:0] out
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);
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logic [7:0] ff;
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always_ff @(posedge clk) ff <= in + 8'd2;
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assign out = ff;
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endmodule
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`endif
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