125 lines
2.2 KiB
Plaintext
125 lines
2.2 KiB
Plaintext
$version Generated by VerilatedVcd $end
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$timescale 1ps $end
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$scope module top $end
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$var wire 1 " clk $end
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$var wire 1 # reset_l $end
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$scope module t $end
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$var wire 1 " clk $end
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$var wire 1 # reset_l $end
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$scope module u0_sub_top $end
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$var wire 1 $ clk $end
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$var wire 1 % reset_l $end
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$scope module u0 $end
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$var wire 1 & clk $end
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$var wire 1 ' reset_l $end
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$upscope $end
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$scope module u1 $end
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$var wire 1 ( clk $end
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$var wire 1 ) reset_l $end
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$upscope $end
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$scope module u2 $end
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$var wire 1 * clk $end
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$var wire 1 + reset_l $end
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$upscope $end
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$scope module u3 $end
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$var wire 1 , clk $end
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$var wire 1 - reset_l $end
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$upscope $end
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$scope module u4 $end
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$var wire 1 . clk $end
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$var wire 1 / reset_l $end
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$upscope $end
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$scope module u5 $end
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$var wire 1 0 clk $end
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$var wire 1 1 reset_l $end
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$upscope $end
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$scope module u6 $end
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$var wire 1 2 clk $end
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$var wire 1 3 reset_l $end
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$upscope $end
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$scope module u7 $end
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$var wire 1 4 clk $end
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$var wire 1 5 reset_l $end
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$upscope $end
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$upscope $end
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$scope module u1_sub_top $end
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$var wire 1 6 clk $end
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$var wire 1 7 reset_l $end
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$scope module u0 $end
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$var wire 1 8 clk $end
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$var wire 1 9 reset_l $end
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$upscope $end
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$scope module u1 $end
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$var wire 1 : clk $end
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$var wire 1 ; reset_l $end
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$upscope $end
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$scope module u2 $end
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$var wire 1 < clk $end
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$var wire 1 = reset_l $end
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$upscope $end
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$scope module u3 $end
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$var wire 1 > clk $end
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$var wire 1 ? reset_l $end
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$upscope $end
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$scope module u4 $end
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$var wire 1 @ clk $end
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$var wire 1 A reset_l $end
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$upscope $end
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$scope module u5 $end
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$var wire 1 B clk $end
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$var wire 1 C reset_l $end
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$upscope $end
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$scope module u6 $end
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$var wire 1 D clk $end
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$var wire 1 E reset_l $end
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$upscope $end
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$scope module u7 $end
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$var wire 1 F clk $end
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$var wire 1 G reset_l $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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0"
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0#
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0$
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0%
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06
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07
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0&
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0'
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0(
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0)
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0*
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0+
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0,
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0-
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0.
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0/
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00
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01
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02
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03
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04
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05
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08
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09
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0:
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0;
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0<
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0=
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0>
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0?
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0@
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0A
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0B
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0C
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0D
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0E
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0F
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0G
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