132 lines
2.3 KiB
Plaintext
132 lines
2.3 KiB
Plaintext
$date
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Sat Mar 14 09:16:58 2026
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$end
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$version
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Generated by VerilatedFst
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$end
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$timescale
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1ps
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$end
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$scope module top $end
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$var wire 1 ! clk $end
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$var wire 1 " reset_l $end
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$scope module t $end
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$var wire 1 ! clk $end
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$var wire 1 " reset_l $end
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$scope module u0_sub_top $end
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$var wire 1 # clk $end
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$var wire 1 $ reset_l $end
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$scope module u0 $end
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$var wire 1 % clk $end
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$var wire 1 & reset_l $end
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$upscope $end
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$scope module u1 $end
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$var wire 1 ' clk $end
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$var wire 1 ( reset_l $end
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$upscope $end
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$scope module u2 $end
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$var wire 1 ) clk $end
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$var wire 1 * reset_l $end
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$upscope $end
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$scope module u3 $end
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$var wire 1 + clk $end
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$var wire 1 , reset_l $end
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$upscope $end
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$scope module u4 $end
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$var wire 1 - clk $end
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$var wire 1 . reset_l $end
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$upscope $end
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$scope module u5 $end
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$var wire 1 / clk $end
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$var wire 1 0 reset_l $end
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$upscope $end
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$scope module u6 $end
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$var wire 1 1 clk $end
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$var wire 1 2 reset_l $end
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$upscope $end
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$scope module u7 $end
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$var wire 1 3 clk $end
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$var wire 1 4 reset_l $end
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$upscope $end
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$upscope $end
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$scope module u1_sub_top $end
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$var wire 1 5 clk $end
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$var wire 1 6 reset_l $end
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$scope module u0 $end
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$var wire 1 7 clk $end
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$var wire 1 8 reset_l $end
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$upscope $end
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$scope module u1 $end
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$var wire 1 9 clk $end
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$var wire 1 : reset_l $end
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$upscope $end
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$scope module u2 $end
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$var wire 1 ; clk $end
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$var wire 1 < reset_l $end
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$upscope $end
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$scope module u3 $end
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$var wire 1 = clk $end
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$var wire 1 > reset_l $end
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$upscope $end
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$scope module u4 $end
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$var wire 1 ? clk $end
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$var wire 1 @ reset_l $end
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$upscope $end
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$scope module u5 $end
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$var wire 1 A clk $end
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$var wire 1 B reset_l $end
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$upscope $end
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$scope module u6 $end
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$var wire 1 C clk $end
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$var wire 1 D reset_l $end
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$upscope $end
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$scope module u7 $end
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$var wire 1 E clk $end
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$var wire 1 F reset_l $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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0F
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0E
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0D
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0C
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0B
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0A
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0@
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0?
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0>
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0=
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0<
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0;
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0:
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09
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08
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07
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06
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05
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04
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03
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02
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01
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00
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0/
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0.
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0-
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0,
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0+
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0*
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0)
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0(
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0'
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0&
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0%
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0$
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0#
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0"
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0!
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