33 lines
922 B
Systemverilog
33 lines
922 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2022 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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module top;
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logic v;
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int num;
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time t;
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initial begin
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num = 1;
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#1;
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if (v) $stop;
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num = 21;
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t = $time;
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// Zero delay should postpone the execution and resume it after
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// evaluating combinational logic which would update `v`. However,
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// currently we can't postpone the resumption in the current timeframe
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// past the combinatorial logic evaluation as that is intertwined with
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// NBA evaluation and partitioned for multithreading. This causes `v`
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// to not have its value updated despite being checked after #0 delay.
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#0;
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if (!v) $stop;
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if (t != $time) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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always_comb v = (num == 21);
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endmodule
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