66 lines
1.2 KiB
Systemverilog
66 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Paul Wright
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// SPDX-License-Identifier: CC0-1.0
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module t;
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timeunit 1ns; timeprecision 1ps;
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logic clkb, clk;
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initial begin
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clkb = 0;
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end
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always @(clk) begin
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clkb <= ~clk;
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end
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bot bot (
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.clkb(clkb),
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.clk(clk)
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);
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final begin
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$display("[%g] final (%m)", $realtime());
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end
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endmodule
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module bot (
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input logic clkb,
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output logic clk
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);
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timeunit 1s; timeprecision 1fs;
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integer count;
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real delay;
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initial begin
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count = 0;
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delay = 500e-9;
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clk = clkb;
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#(3.5 * delay) $display("[%g] Initial finishing, clkb = %b", $realtime(), clkb);
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end
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always @(clkb) begin
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$display("[%g] clkb is %b", $realtime(), clkb);
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count++;
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#(delay) clk = clkb;
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end
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always @(count) begin
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if (count > 20) begin
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$display("[%g] Finishing (%m)", $realtime());
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if ($realtime() < (delay * 20)) begin
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$display("[%g] %%Error: That was too quick!", $realtime());
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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final begin
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$display("[%g] final (%m) count was %0d", $realtime(), count);
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end
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endmodule
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