42 lines
844 B
Systemverilog
42 lines
844 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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event a, b;
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int order = 0;
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initial begin
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order++;
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if (order != 1) $stop;
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#10;
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$display("[%0t]%0d -> a", $time, order);
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order++;
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if (order != 2) $stop;
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->a;
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#10;
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$display("[%0t]%0d -> b", $time, order);
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order++;
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if (order != 4) $stop;
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->b;
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#100;
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order++;
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if (order != 6) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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always @(a or b) begin
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$display("[%0t]%0d entering", $time, order);
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order++;
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if (order != 3) $stop;
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#15;
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$display("[%0t]%0d 15 later", $time, order);
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order++;
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if (order != 5) $stop;
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end
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endmodule
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