33 lines
716 B
Systemverilog
33 lines
716 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t;
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task phase();
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#1000;
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$display("ended");
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endtask
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initial begin
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fork
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phase();
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join_none
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#123;
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$display("[%0t] $finish", $time);
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$finish;
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end
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final begin
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$display("[%0t] final", $time);
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`checkd($time, 123);
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end
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endmodule
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