41 lines
867 B
Systemverilog
41 lines
867 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2022 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`ifdef TEST_VERBOSE
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`define WRITE_VERBOSE(args) $write args
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`else
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`define WRITE_VERBOSE(args)
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`endif
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// verilog_format: on
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module t;
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logic clk = 0;
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logic clk_inv;
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int cnt1 = 0;
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int cnt2 = 0;
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always #4 clk = ~clk;
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always @(posedge clk) begin
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cnt1 <= cnt1 + 1;
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`WRITE_VERBOSE(("[%0t] clk (%b)\n", $time, clk));
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end
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assign #2 clk_inv = ~clk;
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initial
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forever begin
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@(posedge clk_inv) cnt2++;
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`WRITE_VERBOSE(("[%0t] clk_inv (%b)\n", $time, clk_inv));
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end
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initial
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#81 begin
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if (cnt1 != 10 && cnt2 != 10) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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