14 lines
379 B
Systemverilog
14 lines
379 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Rather than look at waivers, just check we included it
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`ifndef _VERILATED_STD_WAIVER_VLT_
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`error "Didn't include, no _VERILATED_STD_WAIVER_VLT_"
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`endif
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module t;
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endmodule
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