37 lines
673 B
Systemverilog
37 lines
673 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2022 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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int cyc = 0;
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logic val = 0;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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val = ~val;
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end
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property check(int n);
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disable iff (n == 0) check(
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n - 1
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);
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endproperty
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assert property (@(posedge clk) check(1))
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else begin
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// Assertion should pass
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$write("*-* Assertion failed *-*\n");
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$stop;
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end
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always @(posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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