57 lines
1.5 KiB
Systemverilog
57 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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module t (
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input clk
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);
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int cyc = 0;
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bit rst = 0;
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bit start = 0;
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bit done = 0;
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int fails_a = 0;
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int fails_b = 0;
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// First launch at cyc==2 should be canceled by reset pulse in the middle.
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assert property (@(posedge clk) disable iff (rst) (cyc == 2) |-> ##2 done)
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else fails_a++;
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// Second launch at cyc==8 has no reset pulse in flight and should fail once.
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assert property (@(posedge clk) disable iff (rst) (cyc == 8) |-> ##2 done)
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else fails_b++;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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// Defaults
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start <= 0;
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done <= 0;
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if (cyc == 2) start <= 1;
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if (cyc == 8) start <= 1;
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// Mid-window reset pulse for first launch.
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if (cyc == 3) rst <= 1;
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if (cyc == 4) rst <= 0;
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if (cyc == 16) begin
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`checkd(fails_a, 0);
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`checkd(fails_b, 1);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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