18 lines
403 B
Systemverilog
18 lines
403 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2004 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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// verilator_no_inline_module
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initial begin
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case (1'b1) // synopsys_full_case
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1'b0: $stop;
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1'b1: $finish;
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endcase
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$stop; // Should have failed
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end
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endmodule
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