14 lines
329 B
Systemverilog
14 lines
329 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2019 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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`line
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`line 100
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`line 200 somefile
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`line 300 "somefile 1
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`line 400 "some file"
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`line 500 "somefile" 3
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`line 600 "some file" 3
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