13 lines
395 B
Plaintext
13 lines
395 B
Plaintext
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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`verilator_config
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hier_workers -module "Test" -workers 2
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hier_block -module "Check"
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hier_workers -module "Check" -workers 2
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hier_block -module "CoreHier"
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hier_workers -module "CoreHier" -workers 2
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