117 lines
2.7 KiB
Systemverilog
117 lines
2.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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// Original #6281 reproducer: parameter passed via localparam variable
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// vs. literal constant should resolve to the same specialization.
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// Fixed by ParameterizedHierBlocks::areSame fallback (landed earlier).
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class ClsIntDefault #(
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parameter int P = 32
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);
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function int get_p;
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return P;
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endfunction
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endclass
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// Parameter with byte cast default value
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class ClsByteCast #(
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parameter byte P = byte'(8)
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);
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function byte get_p;
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return P;
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endfunction
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endclass
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// Parameter with int cast default value
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class ClsIntCast #(
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parameter int P = int'(42)
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);
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function int get_p;
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return P;
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endfunction
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endclass
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// Parameter with signed cast default value
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class ClsSignedCast #(
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parameter int P = int'(-5)
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);
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function int get_p;
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return P;
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endfunction
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endclass
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// Module with cast default (cell array test)
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module sub #(
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parameter byte P = byte'(8)
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);
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initial begin
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`checkd(P, 8);
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end
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endmodule
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module t;
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// Original #6281 case: localparam variable vs. literal constant
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localparam int WIDTH = 32;
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ClsIntDefault #(32) orig_a;
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ClsIntDefault #(WIDTH) orig_b;
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// Byte cast default: #() and #(8) should be same type
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ClsByteCast #() byte_a;
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ClsByteCast #(8) byte_b;
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// Int cast default: #() and #(42) should be same type
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ClsIntCast #() int_a;
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ClsIntCast #(42) int_b;
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// Signed cast default: #() and #(-5) should be same type
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ClsSignedCast #() signed_a;
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ClsSignedCast #(-5) signed_b;
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// Multiple instances (template mutation safety)
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ClsByteCast #() multi_a;
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ClsByteCast #(8) multi_b;
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ClsByteCast #() multi_c;
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ClsByteCast #(8) multi_d;
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// Module with cast default
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sub #() sub_default ();
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sub #(8) sub_explicit ();
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initial begin
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orig_a = new;
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orig_b = orig_a;
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`checkd(orig_b.get_p(), 32);
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byte_a = new;
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byte_b = byte_a;
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`checkd(byte_a.get_p(), 8);
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`checkd(byte_b.get_p(), 8);
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int_a = new;
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int_b = int_a;
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`checkd(int_a.get_p(), 42);
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`checkd(int_b.get_p(), 42);
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signed_a = new;
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signed_b = signed_a;
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`checkd(signed_a.get_p(), -5);
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`checkd(signed_b.get_p(), -5);
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multi_a = new;
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multi_b = multi_a;
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multi_c = multi_a;
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multi_d = multi_a;
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`checkd(multi_d.get_p(), 8);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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