134 lines
2.7 KiB
Systemverilog
134 lines
2.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2003 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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// verilator lint_off COMBDLY
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// verilator lint_off LATCH
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// verilator lint_off UNOPT
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// verilator lint_off UNOPTFLAT
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// verilator lint_off MULTIDRIVEN
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reg c1_start;
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initial c1_start = 0;
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wire [31:0] c1_count;
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comb_loop c1 (
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.count(c1_count),
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.start(c1_start)
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);
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wire s2_start = c1_start;
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wire [31:0] s2_count;
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seq_loop s2 (
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.count(s2_count),
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.start(s2_start)
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);
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wire c3_start = (s2_count[0]);
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wire [31:0] c3_count;
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comb_loop c3 (
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.count(c3_count),
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.start(c3_start)
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);
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reg [7:0] cyc;
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initial cyc = 0;
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always @(posedge clk) begin
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//$write("[%0t] %x counts %x %x %x\n", $time,cyc,c1_count,s2_count,c3_count);
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cyc <= cyc + 8'd1;
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case (cyc)
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8'd00: begin
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c1_start <= 1'b0;
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end
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8'd01: begin
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c1_start <= 1'b1;
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end
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default: ;
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endcase
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case (cyc)
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8'd02: begin
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// On Verilator, we expect these comparisons to match exactly,
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// confirming that our settle loop repeated the exact number of
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// iterations we expect. No '$stop' should be called here, and we
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// should reach the normal '$finish' below on the next cycle.
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if (c1_count != 32'h3) $stop;
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if (s2_count != 32'h3) $stop;
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if (c3_count != 32'h3) $stop;
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end
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8'd03: begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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default: ;
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endcase
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end
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endmodule
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module comb_loop ( /*AUTOARG*/
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// Outputs
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count,
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// Inputs
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start
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);
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input start;
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output reg [31:0] count = 0;
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reg [31:0] runnerm1, runner;
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initial runner = 0;
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always @(posedge start) begin
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count = 0;
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runner = 3;
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end
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always @( /*AS*/ runner) begin
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runnerm1 = runner - 32'd1;
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end
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always @( /*AS*/ runnerm1) begin
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if (runner > 0) begin
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count = count + 1;
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runner = runnerm1;
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$write("%m count=%d runner =%x\n", count, runnerm1);
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end
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end
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endmodule
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module seq_loop ( /*AUTOARG*/
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// Outputs
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count,
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// Inputs
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start
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);
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input start;
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output reg [31:0] count;
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initial count = 0;
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reg [31:0] runnerm1, runner;
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initial runner = 0;
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always @(posedge start) begin
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count = 0;
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runner <= 3;
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end
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always @( /*AS*/ runner) begin
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runnerm1 = runner - 32'd1;
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end
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always @( /*AS*/ runnerm1) begin
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if (runner > 0) begin
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count = count + 1;
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runner <= runnerm1;
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$write("%m count=%d runner<=%x\n", count, runnerm1);
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end
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end
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endmodule
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