36 lines
873 B
Systemverilog
36 lines
873 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define check(got,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (got), (exp)); `stop; end while(0)
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// verilog_format: on
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module t;
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int dpiGet = 0;
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function automatic int getDpi();
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return dpiGet;
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endfunction
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export "DPI-C" function getDpi;
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import "DPI-C" context function int getViaDpi(); // calls getDpi()
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int tmp1, tmp2, tmp3;
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initial begin
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dpiGet = 13;
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tmp1 = getViaDpi();
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dpiGet = 14;
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tmp2 = getViaDpi();
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dpiGet = 15;
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tmp3 = getViaDpi();
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`check(tmp1, 13);
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`check(tmp2, 14);
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`check(tmp3, 15);
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end
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endmodule
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