111 lines
2.7 KiB
Systemverilog
111 lines
2.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2003 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc;
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initial cyc = 1;
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// Life analysis checks
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reg [15:0] life;
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// Ding case
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reg [7:0] din;
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reg [15:0] fixin;
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always @* begin
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fixin = {din[7:0], din[7:0]};
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case (din[1:0])
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2'b00: begin
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fixin = {fixin[14:0], 1'b1};
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if (cyc == 101) $display("Prevent ?: optimization a");
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end
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2'b01: begin
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fixin = {fixin[13:0], 2'b11};
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if (cyc == 101) $display("Prevent ?: optimization b");
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end
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2'b10: begin
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fixin = {fixin[12:0], 3'b111};
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if (cyc == 101) $display("Prevent ?: optimization c");
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end
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2'b11: begin
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fixin = {fixin[11:0], 4'b1111};
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if (cyc == 101) $display("Prevent ?: optimization d");
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end
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endcase
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end
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// Remove CResets
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function int f(int in);
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automatic int aut;
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aut = in;
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return aut;
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endfunction
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always @(posedge clk) begin
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if (cyc != 0) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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life = 16'h8000; // Dropped
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life = 16'h0010; // Used below
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if (life != 16'h0010) $stop;
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//
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life = 16'h0020; // Used below
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if ($time < 10000) if (life != 16'h0020) $stop;
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//
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life = 16'h8000; // Dropped
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if ($time > 100000) begin
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if ($time != 0) $stop; // Prevent conversion to ?:
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life = 16'h1030;
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end
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else life = 16'h0030;
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if (life != 16'h0030) $stop;
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//
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life = 16'h0040; // Not dropped, no else below
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if ($time > 100000) life = 16'h1040;
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if (life != 16'h0040) $stop;
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//
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life = 16'h8000; // Dropped
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if ($time > 100000) begin
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life = 16'h1050;
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if (life != 0) $stop; // Ignored, as set is first
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end
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else begin
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if ($time > 100010) life = 16'h1050;
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else life = 16'h0050;
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end
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if (life != 16'h0050) $stop;
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end
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if (cyc == 2) begin
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din <= 8'haa;
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end
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if (cyc == 3) begin
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din <= 8'hfb;
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if (fixin != 16'h5557) $stop;
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end
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if (cyc == 4) begin
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din <= 8'h5c;
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if (fixin != 16'hbfbf) $stop;
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end
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if (cyc == 5) begin
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din <= 8'hed;
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if (fixin != 16'hb8b9) $stop;
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end
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if (cyc == 6) begin
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if (fixin != 16'hb7b7) $stop;
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end
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if (cyc == 8) begin
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if (f(123) != 123) $stop;
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end
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if (cyc == 9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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