71 lines
1.4 KiB
Systemverilog
71 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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class uvm_object;
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endclass
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class uvm_callback;
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endclass
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class uvm_callbacks #(
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type T = uvm_object,
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type CB = uvm_callback
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);
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bit m_registered = 1;
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virtual function bit m_is_registered(uvm_object obj, uvm_callback cb);
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if (m_is_for_me(cb) && m_am_i_a(obj)) begin
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return m_registered;
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end
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endfunction
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virtual function bit m_is_for_me(uvm_callback cb);
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CB this_cb;
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// verilator lint_off WIDTHTRUNC
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return ($cast(this_cb, cb));
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// verilator lint_on WIDTHTRUNC
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endfunction
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virtual function bit m_am_i_a(uvm_object obj);
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T this_t;
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// verilator lint_off WIDTHTRUNC
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return ($cast(this_t, obj));
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// verilator lint_on WIDTHTRUNC
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endfunction
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endclass
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class my_object extends uvm_object;
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endclass
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class my_callback extends uvm_callback;
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endclass
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class other_object extends uvm_object;
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endclass
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module t;
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initial begin
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my_object obj;
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other_object oobj;
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my_callback cb;
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uvm_callbacks #(my_object, my_callback) ucs;
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bit i;
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obj = new;
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oobj = new;
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cb = new;
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ucs = new;
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i = ucs.m_is_registered(obj, cb);
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if (i !== 1) $stop;
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i = ucs.m_is_registered(oobj, cb);
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if (i !== 0) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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