125 lines
2.8 KiB
Systemverilog
125 lines
2.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2013 Sean Moore
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc = 0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [7:0] tripline = crc[7:0];
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/*AUTOWIRE*/
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wire valid;
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wire [3-1:0] value;
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PriorityChoice #(
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.OCODEWIDTH(3)
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) pe (
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.out(valid),
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.outN(value[2:0]),
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.tripline(tripline)
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);
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// Aggregate outputs into a single result vector
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wire [63:0] result = {60'h0, valid, value};
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// Test loop
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
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if (cyc == 0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 64'h0;
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end
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else if (cyc < 10) begin
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sum <= 64'h0;
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end
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else if (cyc < 90) begin
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end
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else if (cyc == 99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'hc5fc632f816568fb
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module PriorityChoice (
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out,
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outN,
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tripline
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);
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parameter OCODEWIDTH = 1;
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localparam CODEWIDTH = OCODEWIDTH - 1;
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localparam SCODEWIDTH = (CODEWIDTH < 1) ? 1 : CODEWIDTH;
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output reg out;
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output reg [OCODEWIDTH-1:0] outN;
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input wire [(1<<OCODEWIDTH)-1:0] tripline;
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wire left;
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wire [SCODEWIDTH-1:0] leftN;
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wire right;
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wire [SCODEWIDTH-1:0] rightN;
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generate
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if (OCODEWIDTH == 1) begin
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assign left = tripline[1];
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assign right = tripline[0];
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always @(*) begin
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out = left || right;
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if (right) begin
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outN = {1'b0};
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end
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else begin
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outN = {1'b1};
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end
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end
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end
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else begin
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PriorityChoice #(
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.OCODEWIDTH(OCODEWIDTH - 1)
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) leftMap (
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.out(left),
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.outN(leftN),
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.tripline(tripline[(2<<CODEWIDTH)-1:(1<<CODEWIDTH)])
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);
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PriorityChoice #(
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.OCODEWIDTH(OCODEWIDTH - 1)
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) rightMap (
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.out(right),
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.outN(rightN),
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.tripline(tripline[(1<<CODEWIDTH)-1:0])
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);
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always @(*) begin
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if (right) begin
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out = right;
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outN = {1'b0, rightN[OCODEWIDTH-2:0]};
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end
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else begin
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out = left;
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outN = {1'b1, leftN[OCODEWIDTH-2:0]};
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end
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end
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end
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endgenerate
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endmodule
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