118 lines
2.5 KiB
Systemverilog
118 lines
2.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2011 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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//
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// bug354
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typedef logic [5:0] data_t;
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module t (
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input clk
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);
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integer cyc = 0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire rst;
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data_t iii_in = crc[5:0];
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data_t jjj_in = crc[11:6];
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data_t iii_out;
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data_t jjj_out;
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logic [1:0] ctl0 = crc[63:62];
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aaa aaa (.*);
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// Aggregate outputs into a single result vector
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wire [63:0] result = {64'h0};
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// Test loop
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
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if (cyc == 0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 64'h0;
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rst <= 1'b0;
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end
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else if (cyc < 10) begin
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sum <= 64'h0;
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rst <= 1'b1;
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end
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else if (cyc < 90) begin
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rst <= 1'b0;
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end
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else if (cyc == 99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'h4afe43fb79d7b71e
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module bbb (
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output data_t ggg_out[1:0],
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input data_t ggg_in[1:0],
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input [1:0][1:0] ctl,
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input logic clk,
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input logic rst
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);
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genvar i;
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generate
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for (i = 0; i < 2; i++) begin : PPP
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always_ff @(posedge clk) begin
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if (rst) begin
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ggg_out[i] <= 6'b0;
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end
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else begin
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if (ctl[i][0]) begin
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if (ctl[i][1]) begin
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ggg_out[i] <= ~ggg_in[i];
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end
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else begin
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ggg_out[i] <= ggg_in[i];
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end
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end
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end
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end
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end
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endgenerate
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endmodule
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module aaa (
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input data_t iii_in,
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input data_t jjj_in,
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input [1:0] ctl0,
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output data_t iii_out,
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output data_t jjj_out,
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input logic clk,
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input logic rst
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);
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// Below is a bug; {} concat isn't used to make arrays
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bbb bbb (
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.ggg_in({jjj_in, iii_in}),
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.ggg_out({jjj_out, iii_out}),
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.ctl({{1'b1, ctl0[1]}, {1'b0, ctl0[0]}}),
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.*
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);
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endmodule
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