verilator/test_regress/t/t_mem_slice_conc_bad.out

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%Error-PROCASSWIRE: t/t_mem_slice_conc_bad.v:44:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'rst'
: ... note: In instance 't'
44 | rst <= 1'b0;
| ^~~
... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest
%Error-PROCASSWIRE: t/t_mem_slice_conc_bad.v:48:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'rst'
: ... note: In instance 't'
48 | rst <= 1'b1;
| ^~~
%Error-PROCASSWIRE: t/t_mem_slice_conc_bad.v:51:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2023 6.5): 'rst'
: ... note: In instance 't'
51 | rst <= 1'b0;
| ^~~
%Error: Exiting due to