17 lines
448 B
Systemverilog
17 lines
448 B
Systemverilog
// This test shall generate a warning, but not an internal error.
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2021 Zhanglei Wang
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// SPDX-License-Identifier: CC0-1.0
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module t_bigmem (
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input wire clk,
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input wire [27:0] addr,
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input wire [255:0] data,
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input wire wen
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);
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reg [(1<<28)-1:0][255:0] mem;
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always @(posedge clk) begin
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if (wen) mem[addr] <= data;
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end
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endmodule
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