75 lines
1.7 KiB
Systemverilog
75 lines
1.7 KiB
Systemverilog
// DESCRIPTION: Verilator: 3-level nested interface typedef with dependent localparams
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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package scp;
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typedef struct packed {
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int unsigned ABits;
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int unsigned BBits;
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} cfg_t;
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endpackage
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// Level 3: innermost interface
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interface a_if #(
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parameter a_p = 0
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) ();
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localparam int LP0 = a_p * 2;
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typedef logic [LP0-1:0] a_t;
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endinterface
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// Level 2: middle interface
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interface sct_if #(
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parameter scp::cfg_t cfg = 0
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) ();
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localparam int LP0 = cfg.ABits * cfg.BBits;
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a_if #(LP0) a_if0 ();
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typedef a_if0.a_t a_t;
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endinterface
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// Level 1: outermost interface
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interface sc_if #(
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parameter scp::cfg_t cfg = 0
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) ();
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sct_if #(cfg) types ();
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typedef types.a_t a_t;
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endinterface
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module sc #(
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parameter scp::cfg_t cfg = 0
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) (
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sc_if io
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);
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typedef io.a_t a_t;
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initial begin
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#1;
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// cfg.ABits=2, cfg.BBits=3 -> LP0=6 -> a_p=6 -> LP0=12 -> a_t is 12 bits
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`checkd(12, $bits(a_t));
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end
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endmodule
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module t;
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localparam scp::cfg_t sc_cfg = '{ABits : 2, BBits : 3};
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sc_if #(sc_cfg) sc_io ();
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sc #(sc_cfg) sc (.io(sc_io));
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initial begin
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#2;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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