87 lines
1.9 KiB
Systemverilog
87 lines
1.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Get agregate type parameter from array of interfaces
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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package p1;
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typedef struct packed {
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int unsigned ABits;
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int unsigned BBits;
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} cfg_t;
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endpackage
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package p2;
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typedef struct packed {
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int unsigned CBits;
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int unsigned DBits;
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} cfg_t;
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endpackage
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interface types_if #(
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parameter p1::cfg_t cfg = 0
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) ();
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localparam int ABits = cfg.ABits;
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localparam int BBits = cfg.BBits;
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typedef struct packed {
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logic [cfg.ABits-1:0] a;
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logic [cfg.BBits-1:0] b;
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} a_t;
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endinterface
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interface io_if #(
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parameter p1::cfg_t cfg = 0
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) ();
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localparam int ABits = cfg.ABits;
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localparam int BBits = cfg.BBits;
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types_if #(cfg) types ();
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typedef types.a_t a_t;
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endinterface
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module modA (
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io_if io
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);
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localparam int ABits = io.types.ABits;
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localparam int BBits = io.types.BBits;
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typedef io.types.a_t a_t;
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initial begin
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#1;
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`checkd(ABits, 8);
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`checkd(BBits, 24);
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`checkd($bits(a_t), 32);
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end
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endmodule
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module t;
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localparam p2::cfg_t mcfg = '{CBits : 8, DBits : 16};
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localparam p1::cfg_t cfg = '{ABits : mcfg.CBits, BBits : mcfg.CBits + mcfg.DBits};
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io_if #(cfg) modA_io ();
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typedef modA_io.types.a_t a_t;
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modA modA_inst (.io(modA_io));
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initial begin
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#2;
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`checkd($bits(a_t), 32);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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