110 lines
2.3 KiB
Systemverilog
110 lines
2.3 KiB
Systemverilog
// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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//
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// DESCRIPTION:
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// Combined test mixing PIN-assigned type param interface (t_interface_derived_type)
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// with nested captured typedef/localparam (t_lparam_dep_iface6).
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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typedef struct packed {
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int unsigned ABits;
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int unsigned BBits;
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} scp_cfg_t;
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interface a_if #(
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parameter a_p = 0
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) ();
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localparam int LP0 = a_p;
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typedef logic [LP0-1:0] a_t;
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endinterface
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interface sct_if #(
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parameter scp_cfg_t cfg = 0
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) ();
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localparam int LP0 = cfg.ABits * cfg.BBits;
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a_if #(LP0) a_if0 ();
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typedef a_if0.a_t a_t;
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endinterface
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interface sc_if #(
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parameter scp_cfg_t cfg = 0
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) ();
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sct_if #(cfg) types ();
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typedef types.a_t a_t;
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endinterface
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interface intf #(
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parameter type data_t = bit,
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parameter int arr[2][4]
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) ();
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data_t data;
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logic [$bits(data)-1:0] other_data;
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endinterface
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module sub #(
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parameter int width,
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parameter int arr[2][4]
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) ();
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typedef struct packed {logic [3:3][0:0][width-1:0] field;} user_type_t;
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intf #(
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.data_t(user_type_t),
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.arr(arr)
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) the_intf ();
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logic [width-1:0] signal;
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always_comb begin
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the_intf.data.field = signal;
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the_intf.other_data = signal;
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end
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endmodule
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module sc #(
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parameter scp_cfg_t cfg = 0
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) (
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sc_if io
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);
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typedef io.a_t a_t;
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initial begin
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#1;
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`checkd($bits(a_t), 6);
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end
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endmodule
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module t (
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input clk
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);
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localparam scp_cfg_t sc_cfg = '{ABits: 2, BBits: 3};
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sc_if #(sc_cfg) sc_io ();
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sc #(sc_cfg) sc_inst (.io(sc_io));
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sub #(
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.width(8),
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.arr('{'{8, 2, 3, 4}, '{1, 2, 3, 4}})
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) sub8 ();
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typedef sc_io.types.a_if0.a_t inner_t;
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typedef sc_io.types.a_t mid_t;
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initial begin
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#1;
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`checkd($bits(inner_t), 6);
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`checkd($bits(mid_t), 6);
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`checkd($bits(sub8.the_intf.data), 8);
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#1;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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