108 lines
3.0 KiB
Systemverilog
108 lines
3.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Get agregate type parameter from array of interfaces
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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package sc;
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typedef struct packed {
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int unsigned CmdTagBits;
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int unsigned Associativity;
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int unsigned Capacity;
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int unsigned LineSize;
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int unsigned StateBits;
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int unsigned AddrBits;
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int unsigned MissQSize;
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// fetch (hit) width. this must be >= to refill width. FgWidth / RefillWidth is the number of array slices for data.
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int unsigned FgWidth;
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// number of expected beats for refill is LineSize/RefillWidth
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int unsigned RefillWidth;
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} cfg_t;
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endpackage
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interface simple_cache_types_if #(
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parameter sc::cfg_t cfg = 0
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) ();
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localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize;
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localparam int SC_LINES_PER_WAY = SC_NUM_LINES / cfg.Associativity;
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localparam int SC_BLOCK_BITS = $clog2(cfg.LineSize);
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localparam int SC_ROW_BITS = $clog2(SC_LINES_PER_WAY);
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localparam int SC_TAG_BITS = cfg.AddrBits - SC_ROW_BITS - SC_BLOCK_BITS;
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localparam int SC_DROWS_PER_LINE = cfg.LineSize / cfg.FgWidth;
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localparam int SC_NUM_DROWS = SC_NUM_LINES * SC_DROWS_PER_LINE;
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endinterface
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interface simple_cache_if #(
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parameter sc::cfg_t cfg = 0
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) ();
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simple_cache_types_if #(cfg) types ();
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endinterface
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module simple_cache #(
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parameter sc::cfg_t cfg = 0
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) (
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simple_cache_if io
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);
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localparam num_rld_beats = cfg.LineSize / cfg.RefillWidth;
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localparam num_arrays = cfg.FgWidth / cfg.RefillWidth;
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localparam dat_array_width = cfg.RefillWidth * 8;
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localparam int SC_DROWS_PER_LINE = io.types.SC_DROWS_PER_LINE;
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localparam int SC_NUM_LINES = io.types.SC_NUM_LINES;
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localparam int SC_LINES_PER_WAY = io.types.SC_LINES_PER_WAY;
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localparam int SC_NUM_DROWS = io.types.SC_NUM_DROWS;
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initial begin
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#1;
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`checkd(SC_DROWS_PER_LINE, 4);
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`checkd(SC_NUM_LINES, 16);
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`checkd(SC_LINES_PER_WAY, 8);
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`checkd(SC_NUM_DROWS, 64);
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`checkd(num_rld_beats, 8);
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`checkd(num_arrays, 2);
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`checkd(dat_array_width, 64);
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end
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endmodule
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module t;
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localparam sc::cfg_t sc_cfg = '{
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CmdTagBits : $clog2(6),
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Associativity : 2,
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Capacity : 1024,
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LineSize : 64,
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StateBits : 2,
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AddrBits : 64,
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MissQSize : 2,
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FgWidth : 16,
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RefillWidth : 8
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};
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simple_cache_if #(sc_cfg) sc_io ();
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simple_cache #(sc_cfg) simple_cache (.io(sc_io));
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localparam int SC_DROWS_PER_LINE = sc_io.types.SC_DROWS_PER_LINE;
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initial begin
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#2;
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`checkd(SC_DROWS_PER_LINE, 4);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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