64 lines
1.7 KiB
Systemverilog
64 lines
1.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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function automatic int ok_unused_func(real val);
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int result = $rtoi(val);
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bit huh = result[0];
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return result + huh;
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endfunction
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// Unused parameter
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function automatic int unused_input_unused_func(
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int not_used); // <-- Warning: UNUSED not_used
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return 5;
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endfunction
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// Undriven variable
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function automatic int undriven_var_unused_func(int some_val);
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int not_driven; // <--- Warning: UNDRIVEN not_driven
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return some_val + not_driven;
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endfunction
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function automatic int undriven_var();
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int undriven_result; // <--- Warning: UNDRIVEN undriven_result
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return undriven_result;
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endfunction
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function automatic int driven_var();
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int driven_result = 3; // Ok
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return driven_result;
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endfunction
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function automatic void undriven_output( //
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output int undriven_out_param); // <-- Warning: UNDRIVEN
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endfunction
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function automatic void untouched_inout( //
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inout int untouched_inout_param); // <--- Warning: UNUSED
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endfunction
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function automatic void untouched_inout_unused_func( //
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inout int untouched_inout_unused_func_param); // <--- Warning: UNUSED
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endfunction
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function automatic void driven_inout_unused_func(inout int driven_inout_unused_func_param);
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driven_inout_unused_func_param = 7;
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endfunction
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function automatic void used_inout_unused_func(inout int used_inout_unused_func_param);
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$display(used_inout_unused_func_param);
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endfunction
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module t;
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int result;
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initial begin
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result = undriven_var();
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undriven_output(result);
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untouched_inout(result);
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$display(result);
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end
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endmodule
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