68 lines
1.3 KiB
Systemverilog
68 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2010 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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`define STRINGIFY(x) `"x`"
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module t ( /*AUTOARG*/
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// Outputs
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out,
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// Inputs
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in
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);
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input in; // inputs don't get flagged as undriven
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output out; // outputs don't get flagged as unused
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sub sub ();
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// Check we don't warn about unused UDP signals
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udp_mux2 udpsub (
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out,
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in,
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in,
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in
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);
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// Check ignoreds mark as used
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reg sysused;
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initial $bboxed(sysused);
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// Check file IO. The fopen is the "driver" all else a usage.
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integer infile;
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integer outfile;
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initial begin
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outfile = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/open.log"}, "w");
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$fwrite(outfile, "1\n");
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$fclose(outfile);
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infile = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/open.log"}, "r");
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if ($fgetc(infile) != "1") begin
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end
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end
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wire _unused_ok;
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endmodule
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module sub;
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wire pub /*verilator public*/; // Ignore publics
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endmodule
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primitive udp_mux2(q, a, b, s);
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output q;
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input a, b, s;
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table
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//a b s : out
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1 ? 0 : 1;
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0 ? 0 : 0;
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? 1 1 : 1;
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? 0 1 : 0;
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0 0 x : 0;
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1 1 x : 1;
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endtable
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endprimitive
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