33 lines
646 B
Systemverilog
33 lines
646 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain.
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// SPDX-FileCopyrightText: 2026 em2machine
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input logic sel,
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input logic sel2,
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input logic d,
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output logic out
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);
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task automatic do_stuff(input logic din);
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out = din;
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endtask
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// Driver #1 (via task call)
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always_comb begin
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out = 1'b0;
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if (sel) do_stuff(d);
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end
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// Driver #2 (separate process)
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// I only want the MULTIDRIVEN.
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/* verilator lint_off LATCH */
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always_comb begin
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if (sel2) out = 1'b1;
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end
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/* verilator lint_on LATCH */
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endmodule
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