20 lines
320 B
Systemverilog
20 lines
320 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2018 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Should have been:
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//module t #(
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module t
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(
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FOO=1
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) (
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output bar
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);
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assign bar = FOO;
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endmodule
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