22 lines
452 B
Systemverilog
22 lines
452 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for Issue#xxxx
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2021 Julien Margetts
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// SPDX-License-Identifier: Unlicense
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module test #(
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parameter W = 65
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) (
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input logic [W-1:0] a,
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input logic e,
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output logic [W-1:0] z
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);
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integer i;
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always @(*)
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if (e) for (i = 0; i < W; i = i + 1) z[i] = a[i];
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else z = W'(0);
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endmodule
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