18 lines
431 B
Systemverilog
18 lines
431 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for issue #2863
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2021 Julien Margetts (Originally provided by Thomas Sailer)
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// SPDX-License-Identifier: Unlicense
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module test (
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input logic [1:0] a,
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input logic e,
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output logic [1:0] z
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);
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always_latch if (e) z[0] = a[0];
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always_latch if (e) z[1] = a[1];
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endmodule
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