34 lines
715 B
Systemverilog
34 lines
715 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for issue #2938
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2021 Julien Margetts (Originally provided by YanJiun)
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// SPDX-License-Identifier: Unlicense
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module test (
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input [2:0] a,
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input [3:0] c,
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output reg [7:0] o1,
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output reg [7:0] o2
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);
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integer i;
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always @(*) begin
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case (a)
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{3'b000} : o1 = 8'd1;
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{3'b001} : for (i = 0; i < 4; i = i + 1) o1[i*2+:2] = 2'(c[i]);
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{3'b010} : o1 = 8'd3;
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{3'b011} : o1 = 8'd4;
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default: o1 = 0;
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endcase
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end
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always_comb begin
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unique if (a[0]) o2 = 1;
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else if (a[1]) o2 = 2;
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else o2 = 3;
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end
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endmodule
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