20 lines
384 B
Systemverilog
20 lines
384 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for issue #1609
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Julien Margetts
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// SPDX-License-Identifier: Unlicense
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module t ( /*AUTOARG*/
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a,
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b,
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o
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);
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input a;
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input b;
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output reg o;
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// verilator lint_off LATCH
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always @(a or b) if (a) o <= b;
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endmodule
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