13 lines
298 B
Systemverilog
13 lines
298 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2010 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input wire i,
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input wire i2 = i // Good under IEEE 1800-2009
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);
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endmodule
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