41 lines
605 B
Systemverilog
41 lines
605 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2008 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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logic oe;
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read r (
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.clk(clk),
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.data(((oe == 1'd001) && implicit_write))
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);
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sets s (
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.clk(clk),
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.enable(implicit_write)
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);
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read u (
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.clk(clk),
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.data(~implicit_also)
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);
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endmodule
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module sets (
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input clk,
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output enable
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);
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assign enable = 1'b0;
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endmodule
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module read (
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input clk,
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input data
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);
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endmodule
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