35 lines
649 B
Systemverilog
35 lines
649 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2017 Josh Redford
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// SPDX-License-Identifier: CC0-1.0
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interface my_if;
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logic valid;
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logic [7:0] data;
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modport slave_mp(input valid, input data);
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modport master_mp(output valid, output data);
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endinterface
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module t (
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input wire clk,
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my_if.slave_mp in_if,
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my_if.master_mp out_if
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);
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my_if my_i ();
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always @(posedge clk) begin
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my_i.valid <= in_if.valid;
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my_i.data <= in_if.data;
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end
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assign out_if.valid = my_i.valid;
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assign out_if.data = my_i.data;
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endmodule
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