20 lines
370 B
Systemverilog
20 lines
370 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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wire clk;
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let letf(x) = (x << 1);
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always @(posedge clk) begin
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case (0)
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0: letf(0); // Bad, need a statement
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endcase
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end
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endmodule
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