53 lines
1.0 KiB
Systemverilog
53 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// A test of the +verilog1995ext+ and +verilog2001ext+ flags.
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//
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// This source code contains constructs that are valid in Verilog 2001 and
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// SystemVerilog 2005/2009, but not in Verilog 1995. So it should fail if we
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// set the language to be 1995, but not 2001.
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//
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// Compile only test, so no need for "All Finished" output.
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2012 Jeremy Bennett
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// SPDX-License-Identifier: CC0-1.0
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module t (
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// Inputs
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clk
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);
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input clk;
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wire [1:0] res;
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// Instantiate the test
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test test_i ( // Outputs
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.res(res[1:0]),
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// Inputs
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.clk(clk),
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.in(1'b1)
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);
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endmodule
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module test ( // Outputs
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res,
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// Inputs
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clk,
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in
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);
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output reg [1:0] res;
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input clk;
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input in;
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// This is a Verilog 2001 test
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generate
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genvar i;
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for (i = 0; i < 2; i = i + 1) begin
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always @(posedge clk) begin
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res[i:i] <= in;
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end
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end
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endgenerate
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endmodule
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