31 lines
435 B
Systemverilog
31 lines
435 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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interface A;
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logic x;
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endinterface
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module B;
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A a ();
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endmodule
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module C (
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A a0,
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A a1
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);
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assign a1.x = a0.x;
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endmodule
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module t;
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B b0 ();
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B b1 ();
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C c (
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b0.a,
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b1.a
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);
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initial $finish;
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endmodule
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